Fintronic Super Finsim v9.2.8 LINUX 英文正式版(線性FinSim Verilog仿真器軟體)
商品名稱： Fintronic Super Finsim v9.2.8 LINUX
商品分類： Linux系統專用軟體
商品類型： 線性FinSim Verilog仿真器軟體
語系版本： 英文正式版
運行平台： LINUX (以民間網站為準)
更新日期： 2007-11-15
熱門標籤： Verilog仿真器軟體
線性FinSim
LINUX
Finsim
Super
Fintronic
破解說明:
1.Install and read \Lz0\install.txt
2.When prompted locate the included keyfile.
內容說明:
Super-FinSim是頂級的線性FinSim Verilog仿真器，從1993年放出第一款FinSim Verilog
仿真器至今，FinSim Verilog已經引入了許多嶄新的遵從：夾雜編譯和解釋型仿真，仿真
工廠大約讓工程師打算數以百計的同步仿真、分離和增量編譯、高堅守保存和重啟、間接
集成C代碼，無須PLI。
英文說明:
Fintronic USA Inc. is a provider of high performance
Electronic Design Automation (EDA) tools. These tools are
crucial for the design of digital circuits. The first step
in the design of a digital circuit is to formally describe
the desired functionality of the circuit in a Hardware
Design Language, such as Verilog HDL. This description of
the circuit is used as input to a simulator which will
enable the designer to find out whether the described
circuit is indeed what is needed. If not, the specification
(in the form of the Verilog description) is modified until
it becomes acceptable. Once satisfied with the
functionality, the designer refines and details this
description to lower levels of abstraction (the "register
transfer level" and the "gate level"), with the ultimate
goal of creating a very simple description of the circuit
which can then be sent to the fabrication facilities where
the actual silicon chips are produced. During this process
of refining the description of the design, the design
engineer has to continue to simulate the circuit to ensure
that the original functionality is still maintained.
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